Job Description

Position: Design Verification Engineer

Location: San Jose/Austin (Onsite/Hybrid)

Position Overview:

• 5+ years of relevant experience in Design Verification.
• Experience with System Verilog and UVM is a must.
• Strong experience in testbench development such as UVM methodology.
• Experience in verification of SerDes IP block interfaces in a complex SoC fabric environment
• Experience in verification of the PCS, PMA SerDes layers and internal SerDes digital backends.

Responsibilities:

• Proficient in System Verilog, UVM testbench development for design verification of complex digital and PHY blocks (in AMS and WREAL modeling verification)
• Proficient in pre-synthesis, and post- place-and-route functional verification (NCSIM, VCS, ModelSim)
• Triage regression failures and make testbench updates.
• Generate and run Testcases on logic simulation models.
• Closely work with Architects and RTL designers.
• Drive Functional Coverage and Code coverage to closure.

Education:

Bachelors Degree in related field.

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