Job Description

Acceler8 Talent is working with a promising new startup creating AI chips specifically designed for certain model types. They're looking for an experienced Design Verification Engineer to join their team. Their first product is focused on transformer models and aims to deliver faster performance with lower latency than typical solutions.

With their custom ASIC technology, you'll have the chance to build applications that aren't possible with standard GPUs—think real-time video generation and advanced deep learning.

Responsibilities:

• Develop and maintain testbenches for ASICs using advanced methodologies, including UVM, to verify microchip functionality.
• Implement System Verilog-based micro-architecture and RTL specifications, maintaining a robust verification environment for AI-focused microchips while considering system-level scenarios and coverage goals.
• Conduct both functional and performance verification, using synthesized netlists, coverage models, and tools like Synopsys VCS and Verdi, ensuring alignment with design requirements.
• Perform timing closure verification, utilizing static timing analysis tools, analyzing outcomes, and identifying corrective actions where necessary.
• Use formal verification tools to ensure equivalency between RTL and gate-level netlists, troubleshooting and collaborating with design teams to resolve any mismatches.
• Develop assertions and checkers at module and chip levels, safeguarding functionality and signal integrity.
• Debug microchips using waveforms and log files, working with design teams to diagnose and resolve root causes of identified issues.
• Automate verification tasks with scripting, using languages like Python for tasks such as testbench generation, test case creation, and result analysis.
• Participate in verification meetings to discuss issues and follow up on required actions, ensuring alignment on verification requirements and progress.
• Document and communicate the verification plan, track progress, and report on coverage analysis for design signoff, maintaining comprehensive records for all verification stages.

Minimum Requirements:

Master’s degree or equivalent in Computer Engineering, Computer Science, Electrical Engineering, or a related field, plus 3 years of experience in a role such as Hardware Engineer II/III, Silicon Engineer III, Sr. Silicon Engineer, ASIC Design Verification Engineer, Staff Design Verification Engineer, or Principal Design Verification Engineer.

Required experience must include at least 4 years in the following areas:

• UVM (Universal Verification Methodology)
• Testbench development
• EDA tool: Synopsys VCS
• System Verilog
• AXI (Advanced eXtensible Interface)
• ASIC Development

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